1 tm fn3105.2 AD7523, ad7533 8-bit, 10-bit multiplying d/a converters the AD7523 and ad7533 are monolithic, low cost, high performance, 8-bit and 10-bit accurate, multiplying digital-to- analog converter (dac), in a 16 pin dip. intersil?s thin film resistors on cmos circuitry provide 10-bit resolution (8-bit accuracy), with ttl/cmos compatible operation. the AD7523 and ad7533?s accurate four quadrant multiplication, full input protection from damage due to static discharge by clamps to v+ and gnd, and very low power dissipation make them very versatile converters. low noise audio gain controls, motor speed controls, digitally controlled gain and digital attenuators are a few of the wide range of applications of the AD7523 and ad7533. functional block diagram features ? 8-bit linearity ? low gain and linearity temperature coefficients ? full temperature range operation ? static discharge input protection ? ttl/cmos compatible ? supply range. . . . . . . . . . . . . . . . . . . . . . . . . +5v to +15v ? fast settling time at 25 o c. . . . . . . . . . . . . . 150ns (max) ? four quadrant multiplication ? ad7533 direct ad7520 equivalent pinout AD7523, ad7533 (pdip) top view msb (4) 20k ? (3) bit 3 bit 2 v ref in 20k ? 20k ? 20k ? 20k ? 20k ? 10k ? 10k ? 10k ? 10k ? spdt nmos 10k ? i out2 (2) i out1 (1) r feedback (15) switches (16) (5) (6) note: switches shown for digital inputs ?high? 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 i out1 i out2 gnd bit 1 (msb) bit 2 bit 3 bit 5 bit 4 r feedback v+ nc/bit 10 nc/bit 9 bit 8 bit 7 bit 6 v ref in (note) (note) note: nc for AD7523 only. ordering information part number number of bits linearity (inl, dnl) temp. range ( o c) package pkg. no. AD7523jn 8 0.2% (8-bit) 0 to 70 16 ld pdip e16.3 ad7533jn 10 0.2% (8-bit) 0 to 70 16 ld pdip e16.3 data sheet january 2001 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a trademark of intersil americas inc. copyright ? intersil americas inc. 2002. all rights reserved
2 absolute maximum ratings thermal information supply voltage (v+ to gnd) . . . . . . . . . . . . . . . . . . . . . . . . . . .+17v v ref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25v digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . v+ to gnd output voltage compliance . . . . . . . . . . . . . . . . . . . . . -100mv to v+ operating conditions temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 o c to 70 o c thermal resistance (typical, note 1) ja ( o c/w) pdip package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 maximum junction temperature (plastic package) . . . . . . . .150 o c maximum storage temperature . . . . . . . . . . . . . . . -65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300 o c caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. note: 1. ja is measured with the component mounted on a low effective thermal conductivity test board in free air. see tech brief tb379 fo r details. electrical specifications v+ = +15v, v ref = +10v, v out1 = v out2 = 0v, unless otherwise specified parameter test conditions AD7523 ad7533 units t a 25 o ct a min-max t a 25 o ct a min-max min max min max min max min max system performance resolution 8-8-10-10-bits nonlinearity -10v v ref +10v, v out1 = v out2 = 0v (notes 2, 3, 6) - 0.2 - 0.2 - 0.2 - 0.2 % of fsr monotonicity guaranteed guaranteed gain error all digital inputs high (note 3) - 1.5 - 1.8 - 1.4 - 1.8 % of fsr nonlinearity tempco -10v v ref + 10v (notes 3, 4) - 2- 2- 2- 2 ppm of fsr/ o c gain error tempco - 10 - 10 - 10 - 10 ppm of fsr/ o c output leakage current (either output) v out1 = v out2 = 0 - 50 - 200 - 50 - 200 na dynamic characteristics power supply rejection v+ = 14.0v to 15.0v (note 3) - 0.02 - 0.03 - 0.005 - 0.008 % of fsr/% of ? v+ output current settling time to 0.2% of fsr, r l = 100 ? (note 4) - 150 - 200 - 600 - 800 ns feedthrough error v ref = 20v p-p , 200khz sine wave, all digital inputs low (note 4) - 1/2 - 1- 0.05 - 0.1 lsb reference inputs input resistance (pin 15) all digital inputs high i out1 at ground (note 4) 5-5-5-5-k ? -20-20-20-20k ? temperature coefficient - -500 - -500 - -300 - -300 ppm/ c AD7523, ad7533
3 definition of terms nonlinearity: error contributed by deviation of the dac transfer function from a ?best straight line? through the actual plot of transfer function. normally expressed as a percentage of full scale range or in (sub)multiples of 1 lsb. resolution: it is addressing the smallest distinct analog output change that a d/a converter can produce. it is commonly expressed as the number of converter bits. a converter with resolution of n bits can resolve output changes of 2 -n of the full-scale range, e.g., 2 -n v ref for a unipolar conversion. resolution by no means implies linearity. settling time: time required for the output of a dac to settle to within specified error band around its final value (e.g., 1 / 2 lsb) for a given digital input change, i.e., all digital inputs low to high and high to low. gain error: the difference between actual and ideal analog output values at full-scale range, i.e., all digital inputs at high state. it is expressed as a percentage of full scale range or in (sub)multiples of 1 lsb. feedthrough error: error caused by capacitive coupling from v ref to i out1 with all digital inputs low. output capacitance: capacitance from i out1 , and i out2 terminals to ground. output leakage current: current which appears on i out1 , terminal when all digital inputs are low or on i out2 terminal when all digital inputs are high. for further information on the use of this device, see the following application notes: analog output output capacitance c out1 all digital inputs high (note 4) - 100 - 100 - 100 - 100 pf c out2 - 30 - 30 - 35 - 35 pf c out1 all digital inputs low (note 4) - 30 - 30 - 35 - 35 pf c out2 - 100 - 100 - 100 - 100 pf digital inputs low state threshold, v il -0.8-0.8-0.8-0.8 v high state threshold, v ih 2,4 - 2,4 - 2.4 - 2.4 - v input current (low or high), i il , i ih v in = 0v or + 15v - 1- 1- 1- 1 a input coding see tables 1 through 3 binary/offset binary binary/offset binary input capacitance (note 4) - 4 - 4 - 4 - 4 pf power supply characteristics power supply voltage range (note 6) +5 to +16 +5 to +16 v i+ all digital inputs high or low (excluding ladder network) -2-2.5-2-2.5ma notes: 2. full scale range (fsr) is 10v for unipolar and 10v for bipolar modes. 3. using internal feedback resistor, r feedback . 4. guaranteed by design or characterization and not production tested. 5. accuracy not guaranteed unless outputs at ground potential. 6. accuracy is tested and guaranteed at v+ = +15v, only. electrical specifications v+ = +15v, v ref = +10v, v out1 = v out2 = 0v, unless otherwise specified (continued) parameter test conditions AD7523 ad7533 units t a 25 o ct a min-max t a 25 o ct a min-max min max min max min max min max application notes note # description an002 ?principles of data acquisition and conversion? an018 ?do?s and don?ts of applying a/d converters? an042 ?interpretation of data conversion accuracy specifications? AD7523, ad7533
4 detailed description the AD7523 and ad7533 are monolithic multiplying d/a converters. a highly stable thin film r-2r resistor ladder network and nmos spdt switches form the basis of the converter circuit, cmos level shifters permit low power ttl/cmos compatible operation. an external voltage or current reference and an operational amplifier are all that is required for most voltage output applications. a simplified equivalent circuit of the dac is shown in the functional diagram. the nmos spdt switches steer the ladder leg currents between i out1 and i out2 buses which must be held at ground potential. this configuration maintains a constant current in each ladder leg independent of the input code. converter errors are further reduced by using separate metal interconnections between the major bits and the outputs. use of high threshold switches reduce offset (leakage) errors to a negligible level. the level shifter circuits are comprised of three inverters with positive feedback from the output of the second to the first, see figure 1. this configuration results in ttl/cmos compatible operation over the full military temperature range. with the ladder spdt switches driven by the level shifter, each switch is binarily weighted for an on resistance proportional to the respective ladder leg current. this assures a constant voltage drop across each switch, creating equipotential terminations for the 2r ladder resistors and high accurate leg currents. typical applications unipolar binary operation - AD7523 (8-bit dac) the circuit configuration for operating the AD7523 in unipolar mode is shown in figure 2. with positive and negative v ref values the circuit is capable of 2-quadrant multiplication. the ?digital input code/analog output value? table for unipolar mode is given in table 1. zero offset adjustment 1. connect all digital inputs to gnd. 2. adjust the offset zero adjust trimpot of the output operational amplifier for 0v 1mv (max) at v out . gain adjustment 1. connect all digital inputs to v+. 2. monitor v out for a -v ref (1 1 / 2 8 ) reading. 3. to increase v out , connect a series resistor, r2, (0 ? to 250 ? ) in the i out1 amplifier feedback loop. 4. to decrease v out , connect a series resistor, r1, (0 ? to 250 ? ) between the reference voltage and the v ref terminal. unipolar binary operation - ad7533 (10-bit dac) the circuit configuration for operating the ad7533 in unipolar mode is shown in figure 2. with positive and negative v ref values the circuit is capable of 2-quadrant multiplication. the ?digital input code/analog output value? table for unipolar mode is given in table 2. v+ ttl/ cmos input 13 4 5 6 7 2 89 to ladder i out2 i out1 figure 1. cmos switch table 1. unlpolar binary code - AD7523 digital input msb lsb analog output (v out ) 11111111 10000001 10000000 01111111 00000001 00000000 notes: 9. . 15 16 1 4 11 3 2 AD7523/ msb lsb 14 +15v v ref gnd out1 out2 6 v out - + r feedback data inputs ad7533 10v r2 cr1 notes: 7. r1 and r2 used only if gain adjustment is required. 8. cr1 protects AD7523 and ad7533 against negative transients. figure 2. unipolar binary operation r1 v ref 255 256 --------- - ?? ?? ? v ref 129 256 --------- - ?? ?? ? v ref 128 256 --------- - ?? ?? ? v ref 2 ---------------- - ? = v ref 127 256 --------- - ?? ?? ? v ref 1 256 --------- - ?? ?? ? v ref 0 256 --------- - ?? ?? ? 0 = 1lsb 2 8 ? () v ref () 1 256 --------- - ?? ?? v ref () == AD7523, ad7533
5 zero offset adjustment 5. connect all digital inputs to gnd. 6. adjust the offset zero adjust trimpot of the output operational amplifier for 0v 1mv (max) at v out . gain adjustment 1. connect all digital inputs to v+. 2. monitor v out for a -v ref (1 - 1/2 10 ) reading. 3. to increase v out , connect a series resistor, r2, (0 ? to 250 ? ) in the i out1 amplifier feedback loop. 4. to decrease v out , connect a series resistor, r1, (0 ? to 250 ? ) between the reference voltage and the v ref terminal. bipolar (offset binary) operation - AD7523 the circuit configuration for operating the AD7523 in the bipolar mode is given in figure 3. using offset binary digital input codes and positive and negative reference voltage values, four-quadrant multiplication can be realized. the ?digital input code/analog output value? table for bipolar mode is given in table 3.) a ?logic 1? input at any digital input forces the corresponding ladder switch to steer the bit current to i out1 bus. a ?logic 0? input forces the bit current to i out2 bus. for any code the i out1 and i out2 bus currents are complements of one another. the current amplifier at i out2 changes the polarity of i out2 current and the transconductance amplifier at i out output sums the two currents. this configuration doubles the output range. the difference current resulting at zero offset binary code, (msb = ?logic 1?, all other bits = ?logic 0?), is corrected by using an external resistor, (10m ? ), from v ref to i out2 (figure 3). offset adjustment 1. adjust v ref to approximately +10v. 2. connect all digital inputs to ?logic 1?. 3. adjust i out2 amplifier offset adjust trimpot for 0v 1mv at i out2 amplifier output. 4. connect msb (bit 1) to ?logic 1? and all other bits to ?logic 0?. 5. adjust i out1 amplifier offset adjust trimpot for 0v 1mv at v out . gain adjustment 1. connect all digital inputs to v+. 2. monitor v out for a -v ref (1 1 / 2 8 ) volts reading. 3. to increase v out , connect a series resistor, r2, of up to 250 ? between v out and r feedback . 4. to decrease v out , connect a series resistor, r1, of up to 250 ? between the reference voltage and the v ref terminal. bipolar (offset binary) operation - ad7533 the circuit configuration for operating the ad7533 in the bipolar mode is given in figure 3. using offset binary digital input codes and positive and negative reference voltage values, 4-quadrant multiplication can be realized. the ?digital input code/analog output value? table for bipolar mode is given in table 4. a ?logic 1? input at any digital input forces the corresponding ladder switch to steer the bit current to i out1 bus. a ?logic 0? input forces the bit current to i out2 bus. for any code the i out1 and i out2 bus currents are complements of one another. the current amplifier at i out2 changes the polarity of i out2 current and the transconductance amplifier at i out1 output sums the two currents. this configuration doubles the output range. the difference current resulting at zero offset binary code, (msb = ?logic 1?, all other bits = ?logic 0?), is corrected by using an external resistor, (10m ? ), from v ref to i out2 . table 2. unlpolar binary code - ad7533 digital input msb lsb (note 10) nominal analog output 1111111111 1000000001 1000000000 0111111111 0000000001 0000000000 notes: 10. v out as shown in figure 2. 11. nominal full scale for the circuit of figure 2 is given by: . 12. nominal lsb magnitude for the circuit of figure 2 is given by: . v ref 1023 1024 ------------ - ?? ?? ? v ref 513 1024 ------------ - ?? ?? ? v ref 512 1024 ------------ - ?? ?? ? v ref 2 --------------- ? = v ref 511 1024 ------------ - ?? ?? ? v ref 1 1024 ------------ - ?? ?? ? v ref 0 1024 ------------ - ?? ?? ? 0 = fs v ref 1023 1024 ------------ - ?? ?? ? = lsb v ref 1 1024 ------------ - ?? ?? = table 3. blpolar (offset binary) code - AD7523 digital input msb lsb analog output 11111111 10000001 10000000 0 01111111 00000001 00000000 notes: 13. . v ref 127 128 --------- - ?? ?? ? v ref 1 128 --------- - ?? ?? ? +v ref 1 128 --------- - ?? ?? +v ref 127 128 --------- - ?? ?? +v ref 128 128 --------- - ?? ?? 1lsb 2 7 ? () v ref () 1 128 --------- - ?? ?? v ref () == AD7523, ad7533
6 offset adjustment 5. adjust v ref to approximately +10v. 6. connect all digital inputs to ?logic 1?. 7. adjust i out2 amplifier offset adjust trimpot for 0v 1mv at i out2 amplifier output. 8. connect msb (bit 1) to ?logic 1? and all other bits to ?logic 0?. 9. adjust i out1 amplifier offset adjust trimpot for 0v 1mv at v out . gain adjustment 1. connect all digital inputs to v+. 2. monitor v out for a -v ref (1 - 2 -9 ) volts reading. 3. to increase v out , connect a series resistor (r2) of up to 250 ? between v out and r feedback . 4. to decrease v out , connect a series resistor (r1) of up to 250 ? between the reference voltage and the v ref terminal. i out2 6 r feedback 6 - + i out1 cr1 15 16 1 4 13 3 2 AD7523/ msb lsb 14 +15v v ref data inputs ad7533 10v r3 5k r4 5k v out r2 cr2 r1 r6 10m ? figure 3. bipolar operation (4-quadrant multiplication) - + table 4. unlpolar binary code - ad7533 digital input msb lsb (note 14) nominal analog output 1111111111 1000000001 1000000000 0 0111111111 0000000001 0000000000 notes: 14. v out as shown in figure 3. 15. nominal full scale for the circuit of figure 3 is given by: . 16. nominal lsb magnitude for the circuit of figure 3 is given by: . -v ref 511 512 --------- - ?? ?? -v ref 1 512 --------- - ?? ?? +v ref 1 512 --------- - ?? ?? +v ref 511 512 --------- - ?? ?? +v ref 512 512 --------- - ?? ?? fsr v ref 1023 512 ------------ - ?? ?? = lsb v ref 1 512 --------- - ?? ?? = AD7523, ad7533
7 figure 4. 10-bit and sign multiplying dac out2 6 - + r feedback 6 - + out1 15 16 1 4 13 3 2 ad7533 msb lsb 14 v+ v ref magnitude bits 10v v out 10k gnd sign bit digital input bipolar analog input 10k 1 / 2 ih5140 5k figure 5. programmable function generator v out = -v in/d where: figure 6. divider (digitally controlled gain) figure 7. modified scale factor and offset 6 - + out1 15 16 1 4 13 3 2 AD7523/ msb lsb 14 nc digital frequency control word ad7533 +15v v dd a1 c1 calibrate 10k 6.8v (2) 6 - + a2 10k 1% 10k 1% 4.7k triangular wave square wave 1k out2 6 - + out2 14 24 11 3 1 AD7523/ msb lsb 16 +15v v in digital input ad7533 15 bit 8 (10) (ad7533) bit 1 ?d? v ref v out out1 r fb d bit 1 2 1 ------------- bit 2 2 2 ------------- bit 8 2 2 ------------- ++ = 0d 255 256 --------- - ? ?? ?? 6 - + 15 16 1 4 13 3 2 AD7523/ msb lsb 14 r1 ad7533 +15v 6 - + bit 1 bit 8 digital input ?d? r2 v ref v out (10) (ad7533) v out v ref r 2 r 1 r 2 + --------------------- - ?? ?? ?? r 1 d r 1 r 2 + --------------------- - ?? ?? ?? ? = where d bit 1 2 1 ----------- - bit 2 2 2 ----------- - bit 8 2 8 ----------- - ++ = 0d 255 256 --------- - ? ?? ?? AD7523, ad7533
8 die characteristics die dimensions 101 mils x 103 mils (2565 m x 2616 m) metallization type: pure aluminum thickness: 10 1k ? passivation type: psg/nitride psg: 7 1.4k ? nitride: 8 1.2k ? process cmos metal gate metallization mask layout AD7523, ad7533 pin 3 gnd pin 2 i out 2 pin 1 i out 1 pin 16 r feedback pin 15 v ref pin 14 v+ nc nc nc nc pin 4 bit 1 (msb) pin 5 bit 2 pin 6 bit 3 pin 7 bit 4 pin 11 bit 8 (lsb) pin 10 bit 7 pin 9 bit 6 pin 8 bit 5 (pin 12, bit 9, ad7533) (pin 13, bit 10, ad7533) AD7523, ad7533
9 all intersil u.s. products are manufactured, assembled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com sales office headquarters north america intersil corporation 7585 irvine center drive suite 100 irvine, ca 92618 tel: (949) 341-7000 fax: (949) 341-7123 intersil corporation 2401 palm bay rd. palm bay, fl 32905 tel: (321) 724-7000 fax: (321) 724-7946 europe intersil europe sarl ave. william graisse, 3 1006 lausanne switzerland tel: +41 21 6140560 fax: +41 21 6140579 asia intersil corporation unit 1804 18/f guangdong water building 83 austin road tst, kowloon hong kong tel: +852 2723 6339 fax: +852 2730 1433 AD7523, ad7533 dual-in-line plastic packages (pdip) notes: 1. controlling dimensions: inch. in case of conflict between english and metric dimensions, the inch dimensions control. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. symbols are defined in the ?mo series symbol list? in section 2.2 of publication no. 95. 4. dimensions a, a1 and l are measured with the package seated in je- dec seating plane gauge gs - 3. 5. d, d1, and e1 dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. e and are measured with the leads constrained to be perpendic- ular to datum . 7. e b and e c are measured at the lead tips with the leads unconstrained. e c must be zero or greater. 8. b1 maximum dimensions do not include dambar protrusions. dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. n is the maximum number of terminal positions. 10. corner leads (1, n, n/2 and n/2 + 1) for e8.3, e16.3, e18.3, e28.3, e42.6 will have a b1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). e a -c- c l e e a c e b e c -b- e1 index 12 3 n/2 n area seating base plane plane -c- d1 b1 b e d d1 a a2 l a1 -a- 0.010 (0.25) c a m bs e16.3 (jedec ms-001-bb issue d) 16 lead dual-in-line plastic package symbol inches millimeters notes min max min max a - 0.210 - 5.33 4 a1 0.015 - 0.39 - 4 a2 0.115 0.195 2.93 4.95 - b 0.014 0.022 0.356 0.558 - b1 0.045 0.070 1.15 1.77 8, 10 c 0.008 0.014 0.204 0.355 - d 0.735 0.775 18.66 19.68 5 d1 0.005 - 0.13 - 5 e 0.300 0.325 7.62 8.25 6 e1 0.240 0.280 6.10 7.11 5 e 0.100 bsc 2.54 bsc - e a 0.300 bsc 7.62 bsc 6 e b - 0.430 - 10.92 7 l 0.115 0.150 2.93 3.81 4 n16 169 rev. 0 12/93
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